1. Field of the Invention
Embodiments of the invention relate to a deposition sequence and related hardware for manufacturing a plug and line typical of a dual damascene structure utilizing a thin conformal barrier layer formed on the walls of the feature.
2. Description of the Related Art
Modern semiconductor integrated circuits usually involve multiple conductive layers separated by dielectric (insulating) layers, such as oxide layers. The conductive layers are electrically interconnected by holes penetrating the intervening oxide layers and contacting some underlying conductive feature. After the holes are etched, they are filled with a metal, typically aluminum or copper, to electrically connect the conductive layers with each other. In a circuit formed by a dual damascene process, there are two types of holes, vias and trenches, which penetrate dielectric layers of the circuit. Vias are holes which extend to an underlying conductive feature. Vias which are filled with a metal are called plugs, or via plugs. Trenches are holes which extend into the dielectric layer of the circuit, but do not extend to an underlying conductive feature. Trenches which are filled with a metal are called lines, which serve as horizontal interconnects in a circuit.
As sizes of features such as holes in integrated circuits continue to decrease, the characteristics of the material forming the plugs become increasingly important. The smaller the plug, the less resistive the material forming the plug should be for speed performance. Copper is a material which is becoming more important as a result. Copper has a resistivity of 1.7 μΩ-cm. Copper has a small RC time constant thereby increasing the speed of a device formed thereof. In addition, copper exhibits improved reliability over aluminum in that copper has excellent electromigration resistance and can drive more current in the lines.
One problem with the use of copper is that copper diffuses into silicon dioxide, silicon and other dielectric materials. Therefore, barrier layers become increasingly important to prevent copper from diffusing into the dielectric materials and compromising the integrity of the device. Barrier materials such as Ta, TaN, SiN, Ti, TiN, W, and WN on the interlayer dielectric will effectively inhibit interlayer diffusion. However, within the same dielectric layer it is difficult to provide an effective barrier to prevent leakage between lines. Several technologies, such as physical vapor deposition (PVD), are presently under investigation for adding a barrier layer to the via sidewall separating the copper metal from the interlayer dielectric. However, common PVD technologies are limited in high aspect structures due to the directional nature of their deposition. Thus, the thickness of a barrier layer deposited by PVD will depend directly upon the structure architecture, with the barrier becoming thinner on the sidewall near the structure bottom. The barrier thickness, and therefore the barrier integrity may be compromised on the sidewall near the structure bottom. Also, the bottom corners of vias often do not form precise right angles at their intersection. Instead, there may be recesses or “undercuts” 11 at the bottom corners of vias 10 formed in a dielectric layer 12, as shown in FIG. 1. As a result, it is difficult to deposit a barrier layer that covers these undercuts by PVD because of the limited directionality of deposition by PVD.
In contrast, chemical vapor deposition (CVD) and atomic layer deposition (ALD) deposited films are, by their nature, conformal in re-entrant structures. Silicon nitride (SixNy) and titanium nitride (TiN) prepared by decomposition of an organic material, tetrakis(dimethylamido) titantium (TDMAT) are common semiconductor manufacturing materials which display the described conformal performance. Both materials are perceived as being good barriers to Cu diffusion, but are considered unattractive due to their high resistivity. The highly resistive nature of these materials detrimentally affects the conductivity between the plug and the underlying conductive features, which must be maintained as low as possible to maximize logic device performance.
Therefore, there is a need for a process sequence and related hardware which provides a good barrier layer on the via sidewall, but which does not negatively affect the conductivity of the plug.